Agilent 16802A 68 Channel Analyzer Card 16911-66403 for Repair

Agilent 16911-66403 68-channel logic analyzer card from a 16802A, sold for repair. The card is only partially functioning.

The 16802A Analysis System Self Test run of 2023/10/25 (full log below) reports 7 failed tests in slot A: Memory Data Bus, Memory Signals, Memory Unload Modes, Dma, HW Accelerated Search, Analyzer Chip Memory Bus, System Clocks (J/K/L/M/Psync). Failures point at memory chip U41 and FPGA U37. Interface FPGA Register, Load Memory FPGAs, Memory FPGA Register, EEPROM, Turbo Clock Divider, System Backplane Clock, Comparators, Inter-chip Resource Bus, Inter-module Flag Bits, Global and Local Arm Lines and both Timing Zoom Memory tests passed.

========== Start of Analysis System Self Test Run ==========
Host machine = a-169xxla2
Instrument = 16802A (1)
Reporting level = 9
———- Execution Details ———-
Start time: 2023/10/25 11:02:08
68-Channel Logic Analyzer(A) running…
Interface FPGA Register Test running…
…Interface FPGA Register Test ended. Result: Passed
Load Memory FPGAs Test running…
…Load Memory FPGAs Test ended. Result: Passed
Memory FPGA Register Test running…
…Memory FPGA Register Test ended. Result: Passed
EEPROM Test running…
…EEPROM Test ended. Result: Passed
Memory Data Bus Test running…
Slot A, Data Failures, nChip 0, Bonus port, exp=05555501, act=05A55501, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=00000002, act=00020000, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=05555502, act=05A55502, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=00000004, act=00040000, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=05555504, act=05A55504, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=00000008, act=00080000, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=05555508, act=05A55508, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=00000010, act=00100000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000020, act=00200000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000040, act=00400000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000080, act=00800000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000100, act=01000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000200, act=02000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000400, act=04000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00000800, act=08000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00001000, act=10000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00002000, act=20000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00004000, act=40000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00008000, act=80000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00020000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00020000, act=00000002, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00040000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00040000, act=00000004, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00080000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00080000, act=00000008, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00100000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00100000, act=00000010, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00200000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00200000, act=00000020, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00400000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00400000, act=00000040, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00800000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=00800000, act=00000080, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=01000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=01000000, act=00000100, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=02000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=02000000, act=00000200, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=04000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=04000000, act=00000400, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=08000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=08000000, act=00000800, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=10000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=10000000, act=00001000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=20000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=20000000, act=00002000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=40000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=40000000, act=00004000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=80000000, act=00000000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=80000000, act=00008000, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFFE, act=FFFF0000, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=055555FE, act=05A555FE, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFFD, act=FFFD0001, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=055555FD, act=05A555FD, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFFD, act=FFFDFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFFB, act=FFFB0001, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=055555FB, act=05A555FB, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFFB, act=FFFBFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFF7, act=FFF70001, Mem U41
Slot A, Data Failures, nChip 0, Bonus port, exp=055555F7, act=05A555F7, Mem U38
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFF7, act=FFF7FFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFEF, act=FFEF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFEF, act=FFEFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFDF, act=FFDF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFDF, act=FFDFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFBF, act=FFBF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFFBF, act=FFBFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFF7F, act=FF7F0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFF7F, act=FF7FFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFEFF, act=FEFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFEFF, act=FEFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFDFF, act=FDFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFDFF, act=FDFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFBFF, act=FBFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFFBFF, act=FBFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFF7FF, act=F7FF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFF7FF, act=F7FFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFEFFF, act=EFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFEFFF, act=EFFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFDFFF, act=DFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFDFFF, act=DFFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFBFFF, act=BFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFFBFFF, act=BFFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFF7FFF, act=7FFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFF7FFF, act=7FFFFFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFEFFFF, act=FFFE0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFDFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFDFFFF, act=FFFFFFFD, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFBFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFFBFFFF, act=FFFFFFFB, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFF7FFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFF7FFFF, act=FFFFFFF7, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFEFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFEFFFFF, act=FFFFFFEF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFDFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFDFFFFF, act=FFFFFFDF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFBFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FFBFFFFF, act=FFFFFFBF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FF7FFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FF7FFFFF, act=FFFFFF7F, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FEFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FEFFFFFF, act=FFFFFEFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FDFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FDFFFFFF, act=FFFFFDFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FBFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=FBFFFFFF, act=FFFFFBFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=F7FFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=F7FFFFFF, act=FFFFF7FF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=EFFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=EFFFFFFF, act=FFFFEFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=DFFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=DFFFFFFF, act=FFFFDFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=BFFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=BFFFFFFF, act=FFFFBFFF, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=7FFFFFFF, act=FFFF0001, Mem U41
Slot A, Data Failures, nChip 0, port 3, exp=7FFFFFFF, act=FFFF7FFF, Mem U41
Slot A, Data Error, nChip 0, port 3, bits=FFFEFFFE, Mem U41
…Memory Data Bus Test ended. Result: Failed***
Memory Address Bus Test running…
Initializing Memory…
==================== Operating at center of eyes ====================
———- Count Up 0x00000000 on rows 0x00000000 to 0x00800000 ———-
Writing…
Reading/validating…
Slot A Fpga 0 (U37): Error at ball AE24, Memory chip U41 pin 4
Slot A Fpga 0 (U37): Error at ball AD24, Memory chip U41 pin 5
Slot A Fpga 0 (U37): Error at ball AG30, Memory chip U41 pin 7
Slot A Fpga 0 (U37): Error at ball AE26, Memory chip U41 pin 8
Slot A Fpga 0 (U37): Error at ball AD26, Memory chip U41 pin 10
Slot A Fpga 0 (U37): Error at ball AE28, Memory chip U41 pin 11
Slot A Fpga 0 (U37): Error at ball AE29, Memory chip U41 pin 13
Slot A Fpga 0 (U37): Error at ball AB27, Memory chip U41 pin 54
Slot A Fpga 0 (U37): Error at ball AB28, Memory chip U41 pin 56
Slot A Fpga 0 (U37): Error at ball AB29, Memory chip U41 pin 57
Slot A Fpga 0 (U37): Error at ball AA27, Memory chip U41 pin 59
Slot A Fpga 0 (U37): Error at ball AA29, Memory chip U41 pin 60
Slot A Fpga 0 (U37): Error at ball AA25, Memory chip U41 pin 62
Slot A Fpga 0 (U37): Error at ball Y25, Memory chip U41 pin 63
Slot A Fpga 0 (U37): Error at ball W25, Memory chip U41 pin 65
Slot A Fpga 0 (U37): Error at ball T25, Memory chip U38 pin 16
Slot A Fpga 0 (U37): Error at ball AH25, Memory chip U38 pin 51
Error mask word: 9 8 7 6 5 4 3 2 1 0
Care mask value: 0fff ffff ffff ffff ffff ffff ffff ffff ffff ffff
Error mask value: 00f0 0000 fffe fffe 0000 0000 0000 0000 0000 0000
Slot A Fpga 0 (U37): Memory subsystem failed.
==================== Failure Summary ====================
———- Slot A Fpga 0 (U37) ———-
———- FPGA 0 ———-
All lines passed.
———- FPGA 1 ———-
…Memory Address Bus Test ended. Result: Passed
Memory Signals Test running…
==================== Operating near left edge of eyes ====================
———- Shift Left 0x00000001 on rows 0x00000000 to 0x00001000 ———-
———- Shift Right 0x7fffffff on rows 0x00000000 to 0x00001000 ———-
———- Count Up 0x00000000 on rows 0x00000000 to 0x00001000 ———-
Error mask value: 00f0 0000 0ffc 0ffe 0000 0000 0000 0000 0000 0000
———- Count Down 0xffffffff on rows 0x00000000 to 0x00001000 ———-
———- Repeat 0x0000ffff on rows 0x00000000 to 0x00001000 ———-
———- Repeat 0xffff0000 on rows 0x00000000 to 0x00001000 ———-
———- Repeat 0x5555aaaa on rows 0x00000000 to 0x00001000 ———-
==================== Operating near right edge of eyes ====================
…Memory Signals Test ended. Result: Failed***
HW Assisted Memory Cell Test running…
…HW Assisted Memory Cell Test ended. Result: Passed
Memory Unload Modes Test running…
Slot A, Chip 0: RAM Data Only Unload Test …
Slot A, Chip 0, RAM U38: MAC:0x000000, nPort 3 MSW, exp:0xfff7 nActual:0x7fff
FAIL: mode=PIO addr=0x6208 sample=0x00000003 word=msw exp=0xfff7 act=0x7fff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000000, nPort 3 LSW, exp:0xffff nActual:0xfffd
FAIL: mode=PIO addr=0x6208 sample=0x00000003 word=lsw exp=0xffff act=0xfffd buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000001, nPort 3 MSW, exp:0xff7f nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=msw exp=0xff7f act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000001, nPort 3 LSW, exp:0xffff nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=lsw exp=0xffff act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000002, nPort 3 MSW, exp:0xf7ff nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x0000000b word=msw exp=0xf7ff act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000003, nPort 3 MSW, exp:0x7fff nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x0000000f word=msw exp=0x7fff act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000004, nPort 3 LSW, exp:0xfff7 nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x00000013 word=lsw exp=0xfff7 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000005, nPort 3 MSW, exp:0xffff nActual:0xfffd
FAIL: mode=PIO addr=0x6208 sample=0x00000017 word=msw exp=0xffff act=0xfffd buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000005, nPort 3 LSW, exp:0xff7f nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x00000017 word=lsw exp=0xff7f act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000006, nPort 3 MSW, exp:0xffff nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x0000001b word=msw exp=0xffff act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000006, nPort 3 LSW, exp:0xf7ff nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x0000001b word=lsw exp=0xf7ff act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000007, nPort 3 MSW, exp:0xffff nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x0000001f word=msw exp=0xffff act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000007, nPort 3 LSW, exp:0x7fff nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x0000001f word=lsw exp=0x7fff act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000008, nPort 3 MSW, exp:0xfffd nActual:0xffdf
FAIL: mode=PIO addr=0x6208 sample=0x00000023 word=msw exp=0xfffd act=0xffdf buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000009, nPort 3 MSW, exp:0xffdf nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x00000027 word=msw exp=0xffdf act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000009, nPort 3 LSW, exp:0xffff nActual:0xfff7
FAIL: mode=PIO addr=0x6208 sample=0x00000027 word=lsw exp=0xffff act=0xfff7 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x00000a, nPort 3 MSW, exp:0xfdff nActual:0xffff
FAIL: mode=PIO addr=0x6208 sample=0x0000002b word=msw exp=0xfdff act=0xffff buf=0x00000000
Slot A, Chip 0: RAM Data Only Unload Test Failed!
Slot A, Chip 0: RAM Count Only Unload Test …
Slot A, Chip 0, RAM U38: MAC:0x000000, nPort 3 MSW, exp:0x0003 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000003 word=msw exp=0x0003 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000000, nPort 3 LSW, exp:0x0000 nActual:0x2003
FAIL: mode=PIO addr=0x6220 sample=0x00000003 word=lsw exp=0x0000 act=0x2003 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000001, nPort 3 MSW, exp:0x0007 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000007 word=msw exp=0x0007 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000001, nPort 3 LSW, exp:0x0000 nActual:0x2007
FAIL: mode=PIO addr=0x6220 sample=0x00000007 word=lsw exp=0x0000 act=0x2007 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000002, nPort 3 MSW, exp:0x000b nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x0000000b word=msw exp=0x000b act=0x0000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000003, nPort 3 MSW, exp:0x000f nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x0000000f word=msw exp=0x000f act=0x0000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000004, nPort 3 MSW, exp:0x0013 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000013 word=msw exp=0x0013 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000004, nPort 3 LSW, exp:0x0000 nActual:0x2013
FAIL: mode=PIO addr=0x6220 sample=0x00000013 word=lsw exp=0x0000 act=0x2013 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000005, nPort 3 MSW, exp:0x0017 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000017 word=msw exp=0x0017 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000005, nPort 3 LSW, exp:0x0000 nActual:0x2017
FAIL: mode=PIO addr=0x6220 sample=0x00000017 word=lsw exp=0x0000 act=0x2017 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000006, nPort 3 MSW, exp:0x001b nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x0000001b word=msw exp=0x001b act=0x0000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000007, nPort 3 MSW, exp:0x001f nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x0000001f word=msw exp=0x001f act=0x0000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000008, nPort 3 MSW, exp:0x0023 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000023 word=msw exp=0x0023 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000008, nPort 3 LSW, exp:0x0000 nActual:0x2023
FAIL: mode=PIO addr=0x6220 sample=0x00000023 word=lsw exp=0x0000 act=0x2023 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000009, nPort 3 MSW, exp:0x0027 nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x00000027 word=msw exp=0x0027 act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000009, nPort 3 LSW, exp:0x0000 nActual:0x2027
FAIL: mode=PIO addr=0x6220 sample=0x00000027 word=lsw exp=0x0000 act=0x2027 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x00000a, nPort 3 MSW, exp:0x002b nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x0000002b word=msw exp=0x002b act=0x0000 buf=0x00000000
Slot A, Chip 0: RAM Count Only Unload Test Failed!
Slot A, Chip 0: Interleaved Data & Count Unload Test …
Slot A, Chip 0, RAM U41: MAC:0x000000, nPort 3 LSW, exp:0x0000 nActual:0x2000
FAIL: mode=PIO addr=0x6220 sample=0x00000001 word=lsw exp=0x0000 act=0x2000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000001, nPort 3 MSW, exp:0x0003 nActual:0xffff
Slot A, Chip 0, RAM U41: MAC:0x000001, nPort 3 LSW, exp:0x0000 nActual:0x2003
Slot A, Chip 0, RAM U38: MAC:0x000002, nPort 3 MSW, exp:0x0005 nActual:0x0001
FAIL: mode=PIO addr=0x6220 sample=0x00000005 word=msw exp=0x0005 act=0x0001 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000003, nPort 3 MSW, exp:0x0007 nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x00000007 word=msw exp=0x0007 act=0x0000 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000004, nPort 3 MSW, exp:0x0009 nActual:0x0001
FAIL: mode=PIO addr=0x6220 sample=0x00000009 word=msw exp=0x0009 act=0x0001 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000004, nPort 3 LSW, exp:0x0000 nActual:0x2008
FAIL: mode=PIO addr=0x6220 sample=0x00000009 word=lsw exp=0x0000 act=0x2008 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000005, nPort 3 MSW, exp:0x000b nActual:0xffff
FAIL: mode=PIO addr=0x6220 sample=0x0000000b word=msw exp=0x000b act=0xffff buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000005, nPort 3 LSW, exp:0x0000 nActual:0x200b
FAIL: mode=PIO addr=0x6220 sample=0x0000000b word=lsw exp=0x0000 act=0x200b buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000006, nPort 3 MSW, exp:0x000d nActual:0x0001
FAIL: mode=PIO addr=0x6220 sample=0x0000000d word=msw exp=0x000d act=0x0001 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000007, nPort 3 MSW, exp:0x000f nActual:0x0000
Slot A, Chip 0, RAM U38: MAC:0x000008, nPort 3 MSW, exp:0x0011 nActual:0x0001
FAIL: mode=PIO addr=0x6220 sample=0x00000011 word=msw exp=0x0011 act=0x0001 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000008, nPort 3 LSW, exp:0x0000 nActual:0x2010
FAIL: mode=PIO addr=0x6220 sample=0x00000011 word=lsw exp=0x0000 act=0x2010 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000009, nPort 3 MSW, exp:0x0013 nActual:0xffff
Slot A, Chip 0, RAM U41: MAC:0x000009, nPort 3 LSW, exp:0x0000 nActual:0x2013
Slot A, Chip 0, RAM U38: MAC:0x00000a, nPort 3 MSW, exp:0x0015 nActual:0x0001
FAIL: mode=PIO addr=0x6220 sample=0x00000015 word=msw exp=0x0015 act=0x0001 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x00000b, nPort 3 MSW, exp:0x0017 nActual:0x0000
FAIL: mode=PIO addr=0x6220 sample=0x00000017 word=msw exp=0x0017 act=0x0000 buf=0x00000000
Slot A, Chip 0: Interleaved Data & Count Unload Test Failed!
Slot A, Chip 0: RAM Data Unload Modes Test Failed!
Slot A, Chip 1: RAM Data Only Unload Test …
Slot A, Chip 1: RAM Count Only Unload Test …
Slot A, Chip 1: Interleaved Data & Count Unload Test …
Slot A, Chip 0: Bad RAMs: U41U38Bad Data: 0xFFFF
…Memory Unload Modes Test ended. Result: Failed***
Dma Test running…
PhysMemSize=0x02000000 NumMemPorts=0x00000004 NumMemBanks=0x00000001
CountPerBank=0x00800000 Formula=PhysMemSize/NumMemPorts/NumMemBanks
DmaSize=0x00001000 Samples=0x00004000 Formula=4*DmaSize
StartAddr=0x007fe800 Formula=CountPerBank-(Samples/2-DmaSize/2)
Slot A, Chip 0, RAM U38: MAC:0x7fe800, nPort 3 MSW, exp:0xfff7 nActual:0xfffd
FAIL: mode=DMA addr=0x6208 sample=0x00000003 word=msw exp=0xfff7 act=0xfffd buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe801, nPort 3 MSW, exp:0xff7f nActual:0xfffd
FAIL: mode=DMA addr=0x6208 sample=0x00000007 word=msw exp=0xff7f act=0xfffd buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe802, nPort 3 MSW, exp:0xf7ff nActual:0xffdf
FAIL: mode=DMA addr=0x6208 sample=0x0000000b word=msw exp=0xf7ff act=0xffdf buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe802, nPort 3 LSW, exp:0xffff nActual:0xffdf
FAIL: mode=DMA addr=0x6208 sample=0x0000000b word=lsw exp=0xffff act=0xffdf buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe803, nPort 3 MSW, exp:0x7fff nActual:0xffdf
FAIL: mode=DMA addr=0x6208 sample=0x0000000f word=msw exp=0x7fff act=0xffdf buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe803, nPort 3 LSW, exp:0xffff nActual:0xffdf
FAIL: mode=DMA addr=0x6208 sample=0x0000000f word=lsw exp=0xffff act=0xffdf buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe804, nPort 3 MSW, exp:0xffff nActual:0xffdf
FAIL: mode=DMA addr=0x6208 sample=0x00000013 word=msw exp=0xffff act=0xffdf buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe804, nPort 3 LSW, exp:0xfff7 nActual:0x1c31
FAIL: mode=DMA addr=0x6208 sample=0x00000013 word=lsw exp=0xfff7 act=0x1c31 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe805, nPort 3 MSW, exp:0xffff nActual:0x37ef
FAIL: mode=DMA addr=0x6208 sample=0x00000017 word=msw exp=0xffff act=0x37ef buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe805, nPort 3 LSW, exp:0xff7f nActual:0x42f7
FAIL: mode=DMA addr=0x6208 sample=0x00000017 word=lsw exp=0xff7f act=0x42f7 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe806, nPort 3 MSW, exp:0xffff nActual:0x33cd
FAIL: mode=DMA addr=0x6208 sample=0x0000001b word=msw exp=0xffff act=0x33cd buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe806, nPort 3 LSW, exp:0xf7ff nActual:0x33cd
FAIL: mode=DMA addr=0x6208 sample=0x0000001b word=lsw exp=0xf7ff act=0x33cd buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe807, nPort 3 MSW, exp:0xffff nActual:0x33cd
FAIL: mode=DMA addr=0x6208 sample=0x0000001f word=msw exp=0xffff act=0x33cd buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe807, nPort 3 LSW, exp:0x7fff nActual:0x33cd
FAIL: mode=DMA addr=0x6208 sample=0x0000001f word=lsw exp=0x7fff act=0x33cd buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe808, nPort 3 MSW, exp:0xfffd nActual:0x33cd
FAIL: mode=DMA addr=0x6208 sample=0x00000023 word=msw exp=0xfffd act=0x33cd buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe809, nPort 3 MSW, exp:0xffdf nActual:0x77dd
FAIL: mode=DMA addr=0x6208 sample=0x00000027 word=msw exp=0xffdf act=0x77dd buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe809, nPort 3 LSW, exp:0xffff nActual:0xbfff
FAIL: mode=DMA addr=0x6208 sample=0x00000027 word=lsw exp=0xffff act=0xbfff buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe800, nPort 3 MSW, exp:0x0003 nActual:0xffff
FAIL: mode=DMA addr=0x6220 sample=0x00000003 word=msw exp=0x0003 act=0xffff buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe800, nPort 3 LSW, exp:0x0000 nActual:0x3083
FAIL: mode=DMA addr=0x6220 sample=0x00000003 word=lsw exp=0x0000 act=0x3083 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe801, nPort 3 MSW, exp:0x0007 nActual:0xffff
FAIL: mode=DMA addr=0x6220 sample=0x00000007 word=msw exp=0x0007 act=0xffff buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe801, nPort 3 LSW, exp:0x0000 nActual:0x3087
FAIL: mode=DMA addr=0x6220 sample=0x00000007 word=lsw exp=0x0000 act=0x3087 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe802, nPort 3 MSW, exp:0x000b nActual:0x0000
FAIL: mode=DMA addr=0x6220 sample=0x0000000b word=msw exp=0x000b act=0x0000 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe803, nPort 3 MSW, exp:0x000f nActual:0x0000
FAIL: mode=DMA addr=0x6220 sample=0x0000000f word=msw exp=0x000f act=0x0000 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe804, nPort 3 MSW, exp:0x0013 nActual:0xffff
FAIL: mode=DMA addr=0x6220 sample=0x00000013 word=msw exp=0x0013 act=0xffff buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe804, nPort 3 LSW, exp:0x0000 nActual:0x17df
FAIL: mode=DMA addr=0x6220 sample=0x00000013 word=lsw exp=0x0000 act=0x17df buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe805, nPort 3 MSW, exp:0x0017 nActual:0x254b
FAIL: mode=DMA addr=0x6220 sample=0x00000017 word=msw exp=0x0017 act=0x254b buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe805, nPort 3 LSW, exp:0x0000 nActual:0x7ca4
FAIL: mode=DMA addr=0x6220 sample=0x00000017 word=lsw exp=0x0000 act=0x7ca4 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe806, nPort 3 MSW, exp:0x001b nActual:0x2288
FAIL: mode=DMA addr=0x6220 sample=0x0000001b word=msw exp=0x001b act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe806, nPort 3 LSW, exp:0x0000 nActual:0x2288
FAIL: mode=DMA addr=0x6220 sample=0x0000001b word=lsw exp=0x0000 act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe807, nPort 3 MSW, exp:0x001f nActual:0x2288
FAIL: mode=DMA addr=0x6220 sample=0x0000001f word=msw exp=0x001f act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe807, nPort 3 LSW, exp:0x0000 nActual:0x2288
FAIL: mode=DMA addr=0x6220 sample=0x0000001f word=lsw exp=0x0000 act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe808, nPort 3 MSW, exp:0x0023 nActual:0xdd77
FAIL: mode=DMA addr=0x6220 sample=0x00000023 word=msw exp=0x0023 act=0xdd77 buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe808, nPort 3 LSW, exp:0x0000 nActual:0xaaab
FAIL: mode=DMA addr=0x6220 sample=0x00000023 word=lsw exp=0x0000 act=0xaaab buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe809, nPort 3 MSW, exp:0x0027 nActual:0x5a97
FAIL: mode=DMA addr=0x6220 sample=0x00000027 word=msw exp=0x0027 act=0x5a97 buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe809, nPort 3 LSW, exp:0x0000 nActual:0xd554
FAIL: mode=DMA addr=0x6220 sample=0x00000027 word=lsw exp=0x0000 act=0xd554 buf=0x09130040
Slot A, Chip 0, RAM U41: MAC:0x7fe800, nPort 3 LSW, exp:0x0000 nActual:0x3800
FAIL: mode=DMA addr=0x6220 sample=0x00000001 word=lsw exp=0x0000 act=0x3800 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe801, nPort 3 MSW, exp:0x0003 nActual:0xffff
Slot A, Chip 0, RAM U41: MAC:0x7fe801, nPort 3 LSW, exp:0x0000 nActual:0x3803
FAIL: mode=DMA addr=0x6220 sample=0x00000003 word=lsw exp=0x0000 act=0x3803 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe802, nPort 3 MSW, exp:0x0005 nActual:0x0001
FAIL: mode=DMA addr=0x6220 sample=0x00000005 word=msw exp=0x0005 act=0x0001 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe803, nPort 3 MSW, exp:0x0007 nActual:0x0000
FAIL: mode=DMA addr=0x6220 sample=0x00000007 word=msw exp=0x0007 act=0x0000 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe804, nPort 3 MSW, exp:0x0009 nActual:0xfffe
FAIL: mode=DMA addr=0x6220 sample=0x00000009 word=msw exp=0x0009 act=0xfffe buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x00000009 word=lsw exp=0x0000 act=0x17df buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe805, nPort 3 MSW, exp:0x000b nActual:0x254b
FAIL: mode=DMA addr=0x6220 sample=0x0000000b word=msw exp=0x000b act=0x254b buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x0000000b word=lsw exp=0x0000 act=0x7ca4 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe806, nPort 3 MSW, exp:0x000d nActual:0x2289
FAIL: mode=DMA addr=0x6220 sample=0x0000000d word=msw exp=0x000d act=0x2289 buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x0000000d word=lsw exp=0x0000 act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe807, nPort 3 MSW, exp:0x000f nActual:0x2288
FAIL: mode=DMA addr=0x6220 sample=0x0000000f word=msw exp=0x000f act=0x2288 buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x0000000f word=lsw exp=0x0000 act=0x2288 buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe808, nPort 3 MSW, exp:0x0011 nActual:0xdd76
FAIL: mode=DMA addr=0x6220 sample=0x00000011 word=msw exp=0x0011 act=0xdd76 buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x00000011 word=lsw exp=0x0000 act=0xaaab buf=0x09130040
Slot A, Chip 0, RAM U38: MAC:0x7fe809, nPort 3 MSW, exp:0x0013 nActual:0x5a97
FAIL: mode=DMA addr=0x6220 sample=0x00000013 word=msw exp=0x0013 act=0x5a97 buf=0x09130040
FAIL: mode=DMA addr=0x6220 sample=0x00000013 word=lsw exp=0x0000 act=0xd554 buf=0x09130040
> Slot A, Chip 0: DMA Unload Modes Test Failed!
…Dma Test ended. Result: Failed***
HW Accelerated Search Test running…
———- Testing FPGA 0 ———-
Slot A Fpga 0 (U37): Failed to find search pattern in memory
Slot A Fpga 0 (U37): Failed test!
———- Testing FPGA 1 ———-
Slot A Fpga 1 (U49): Passed test
…HW Accelerated Search Test ended. Result: Failed***
Chip Registers Read/Write Test running…
==================== Testing Chip 0 ====================
———- Using Pattern 0xa55a ———-
———- Using Pattern 0x5aa5 ———-
———- Using Pattern 0x0000 ———-
———- Using Pattern 0xffff ———-
==================== Testing Chip 1 ====================
==================== Verifying independent chip select lines ====================
…Chip Registers Read/Write Test ended. Result: Passed
Analyzer Chip Memory Bus Test running…
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000001, act=FFFEFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000002, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000004, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000008, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000010, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000020, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000040, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000080, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000100, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000200, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000400, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00000800, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00001000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00002000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00004000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00008000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00010000, act=FFFFFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00020000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00040000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00080000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00100000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00200000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00400000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=00800000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=01000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=02000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=04000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=08000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=10000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=20000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=40000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=80000000, act=FFFEFFFE
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFFD, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFFB, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFF7, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFEF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFDF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFFBF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFF7F, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFEFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFDFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFFBFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFF7FF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFEFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFDFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFFBFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFF7FFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFDFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFFBFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFF7FFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFEFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFDFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FFBFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FF7FFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FEFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FDFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=FBFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=F7FFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=EFFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=DFFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=BFFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Failed, nChip 0, nPort 3, exp=7FFFFFFF, act=FFFFFFFF
Slot A, Analysis Chip Data Bit Error, nChip 0, nPort 3, bits=FFFEFFFE
…Analyzer Chip Memory Bus Test ended. Result: Failed***
LA Chip Calibrations Test running…
…LA Chip Calibrations Test ended. Result: Passed
System Clocks (J/K/L/M/Psync) Test running…
TEST 1: JCLK routed to all chips…
TEST 2: KCLK routed to all chips…
TEST 3: LCLK routed to all chips…
TEST 4: MCLK routed to all chips…
TEST 5: PSYNC A routed to all chips…
Slot A, Chip 0, RAM U38: MAC:0x000000, nPort 3 MSW, exp:0x924c nActual:0xc924
FAIL: mode=PIO addr=0x6208 sample=0x00000003 word=msw exp=0x924c act=0xc924 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000000, nPort 3 LSW, exp:0x4924 nActual:0x4c92
FAIL: mode=PIO addr=0x6208 sample=0x00000003 word=lsw exp=0x4924 act=0x4c92 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000001, nPort 3 MSW, exp:0x24c9 nActual:0x2493
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=msw exp=0x24c9 act=0x2493 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000001, nPort 3 LSW, exp:0x9249 nActual:0xc925
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=lsw exp=0x9249 act=0xc925 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000002, nPort 3 MSW, exp:0x4c92 nActual:0x4924
FAIL: mode=PIO addr=0x6208 sample=0x0000000b word=msw exp=0x4c92 act=0x4924 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000002, nPort 3 LSW, exp:0x2492 nActual:0x4924
FAIL: mode=PIO addr=0x6208 sample=0x0000000b word=lsw exp=0x2492 act=0x4924 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000003, nPort 3 MSW, exp:0xc924 nActual:0x4924
FAIL: mode=PIO addr=0x6208 sample=0x0000000f word=msw exp=0xc924 act=0x4924 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000004, nPort 3 MSW, exp:0x9249 nActual:0x4925
FAIL: mode=PIO addr=0x6208 sample=0x00000013 word=msw exp=0x9249 act=0x4925 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000004, nPort 3 LSW, exp:0x924c nActual:0x2492
FAIL: mode=PIO addr=0x6208 sample=0x00000013 word=lsw exp=0x924c act=0x2492 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000005, nPort 3 MSW, exp:0x2492 nActual:0x9248
FAIL: mode=PIO addr=0x6208 sample=0x00000017 word=msw exp=0x2492 act=0x9248 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000005, nPort 3 LSW, exp:0x24c9 nActual:0x4933
FAIL: mode=PIO addr=0x6208 sample=0x00000017 word=lsw exp=0x24c9 act=0x4933 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000006, nPort 3 MSW, exp:0x4924 nActual:0x2492
FAIL: mode=PIO addr=0x6208 sample=0x0000001b word=msw exp=0x4924 act=0x2492 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000006, nPort 3 LSW, exp:0x4c92 nActual:0x2492
FAIL: mode=PIO addr=0x6208 sample=0x0000001b word=lsw exp=0x4c92 act=0x2492 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000007, nPort 3 MSW, exp:0x9249 nActual:0x2493
FAIL: mode=PIO addr=0x6208 sample=0x0000001f word=msw exp=0x9249 act=0x2493 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000007, nPort 3 LSW, exp:0xc924 nActual:0x2492
FAIL: mode=PIO addr=0x6208 sample=0x0000001f word=lsw exp=0xc924 act=0x2492 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000008, nPort 3 LSW, exp:0x9249 nActual:0x2493
FAIL: mode=PIO addr=0x6208 sample=0x00000023 word=lsw exp=0x9249 act=0x2493 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000009, nPort 3 MSW, exp:0x4932 nActual:0x2492
FAIL: mode=PIO addr=0x6208 sample=0x00000027 word=msw exp=0x4932 act=0x2492 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000009, nPort 3 LSW, exp:0x2492 nActual:0x4924
FAIL: mode=PIO addr=0x6208 sample=0x00000027 word=lsw exp=0x2492 act=0x4924 buf=0x00000000
> Slot A, Chip 0: PSYNC with Chip 9 master Test Failed!
Slot A, Chip 0: Bad RAMs: U41U38Bad Data: 0xFFFE
TEST 6: PSYNC B routed to all chips…
Slot A, Chip 0, RAM U41: MAC:0x000000, nPort 3 LSW, exp:0x4924 nActual:0x9248
FAIL: mode=PIO addr=0x6208 sample=0x00000003 word=lsw exp=0x4924 act=0x9248 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000001, nPort 3 MSW, exp:0x24c9 nActual:0x924d
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=msw exp=0x24c9 act=0x924d buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000001, nPort 3 LSW, exp:0x9249 nActual:0x2493
FAIL: mode=PIO addr=0x6208 sample=0x00000007 word=lsw exp=0x9249 act=0x2493 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000002, nPort 3 MSW, exp:0x4c92 nActual:0x24c8
FAIL: mode=PIO addr=0x6208 sample=0x0000000b word=msw exp=0x4c92 act=0x24c8 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000002, nPort 3 LSW, exp:0x2492 nActual:0x24c8
FAIL: mode=PIO addr=0x6208 sample=0x0000000b word=lsw exp=0x2492 act=0x24c8 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000003, nPort 3 MSW, exp:0xc924 nActual:0x24c8
FAIL: mode=PIO addr=0x6208 sample=0x0000000f word=msw exp=0xc924 act=0x24c8 buf=0x00000000
Slot A, Chip 0, RAM U41: MAC:0x000003, nPort 3 LSW, exp:0x4924 nActual:0x24c8
FAIL: mode=PIO addr=0x6208 sample=0x0000000f word=lsw exp=0x4924 act=0x24c8 buf=0x00000000
Slot A, Chip 0, RAM U38: MAC:0x000004, nPort 3 MSW, exp:0x9249 nActual:0x24c9
FAIL: mode=PIO addr=0x6208 sample=0x00000013 word=msw exp=0x9249 act=0x24c9 buf=0x00000000
> Slot A, Chip 0: PSYNC with Chip 8 master Test Failed!
TEST 7: Each PSYNC routed to half the chips…
> Slot A, Chip 0: PSYNC with both masters Test Failed!
…System Clocks (J/K/L/M/Psync) Test ended. Result: Failed***
Turbo Clock Divider Test running…
TEST 1: Turbo Clock Divider…
…Turbo Clock Divider Test ended. Result: Passed
System Backplane Clock Test running…
Testing 100 MHz – PLL bypass mode:
Slot A, Chip 0: exp: > 9500000, nActual: 9839335
Slot A, Chip 1: exp: > 9500000, nActual: 9835882
Testing PLL at 500 MHz:
Slot A, Chip 0: exp: >47500000, nActual: 51951178
Slot A, Chip 1: exp: >47500000, nActual: 49147246
…System Backplane Clock Test ended. Result: Passed
Comparators Test running…
Check POD0 Thresholds:
Slot A, Chip 0: . …….. …….. . …….. …….. Cal Clk No Act.
Slot A, Chip 1: . …….. …….. . …….. …….. Cal Clk No Act.
Slot A, Chip 0: . …….. …….. . …….. …….. Cal Clk Levels
Slot A, Chip 1: . …….. …….. . …….. …….. Cal Clk Levels
Slot A, Chip 0: . …….. …….. . …….. …….. Cal Clk Activity
Slot A, Chip 1: . …….. …….. . …….. …….. Cal Clk Activity
Check POD1 Thresholds:
Check POD2 Thresholds:
Check POD3 Thresholds:
Slot A, Chip 0: . …….. …….. . …….. …….. Ext Data No Act.
Slot A, Chip 1: . …….. …….. . …….. …….. Ext Data No Act.
Slot A, Chip 0: . …….. …….. . …….. …….. Ext Data Levels
Slot A, Chip 1: . …….. …….. . …….. …….. Ext Data Levels
…Comparators Test ended. Result: Passed
Inter-chip Resource Bus Test running…
ICR Drive Test …
ICR Walking Zeros Test …
…Inter-chip Resource Bus Test ended. Result: Passed
Inter-module Flag Bits Test running…
…Inter-module Flag Bits Test ended. Result: Passed
Global and Local Arm Lines Test running…
…Global and Local Arm Lines Test ended. Result: Passed
Timing Zoom Memory BIST Test running…
…Timing Zoom Memory BIST Test ended. Result: Passed
Timing Zoom Memory Addr/Data Test running…
…Timing Zoom Memory Addr/Data Test ended. Result: Passed
…68-Channel Logic Analyzer(A) ended. Result: Failed***
Stop time: 2023/10/25 11:02:31
———- Problem Summary ———-
The following failures occurred:
68-Channel Logic Analyzer(A) (7 occurrences)
Memory Data Bus Test (Failed in slot A)
Memory Signals Test (Failed in slot A)
Memory Unload Modes Test (Failed in slot A)
Dma Test (Failed in slot A)
HW Accelerated Search Test (Failed in slot A)
Analyzer Chip Memory Bus Test (Failed in slot A)
System Clocks (J/K/L/M/Psync) Test (Failed in slot A)
———- Result Summary ———-
7 tests failed.
See problem summary and execution details above.
========== End of Analysis System Self Test Run ==========

One Agilent 16911-66403 68-channel analyzer card, as shown in the photos.

Not included:
16802A mainframe
Cables and probes

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